1. Field of the Invention
The present invention relates to a power-on-reset circuit, and more specifically to a power-on-reset circuit which can particularly used in a CMOS integrated circuit.
2. Description of Related Art
As the power-on-reset circuit of the prior art, for example, the circuit having a structure disclosed in Japanese Patent Laid-open Publication No. Sho 61-296817 has been well known. The power-on-reset circuit shown in Japanese Patent Laid-open Publication No. Sho 61-296817 is so constituted that an integrating circuit constituted of a resistor and a capacitor is connected in series between a voltage supply terminal and the ground, and an inverter circuit is connected at its input to a node between the resistor and the capacitor and at its output to an output terminal.
Now, an operation of the power-on-reset circuit of the prior art will be described.
Before a voltage is applied to the voltage supply terminal, the output of the inverter circuit is at a low level.
When a voltage is applied to the voltage supply terminal in this condition, the voltage at the node between the resistor and the capacitor rises up at a speed determined by a time constant expressed by the product of the resistance value and the capacitance value of the integrating circuit constituted of the resistor and the capacitor, respectively. In addition, if the potential at the node exceeds a threshold of the inverter circuit, the inverter circuit effects a reverse operation. Thus, the potential of the output terminal brought into a high level from the moment of a powering-on, only for a period determined by a time constant of the integrating circuit, and therefore, a reset signal is outputted only for this period.
As mentioned above, the conventional power-on-reset circuit outputs the reset signal only for a period determined by a time constant of the integrating circuit constituted of a resistor and a capacitor. Therefore, if it is desired to prolong the reset signal output period, it is necessary to use a large resistor having a high resistance value and a large capacitor having a high capacitance value. Thus, a high-integration of the CMOS circuit has been difficult.
Further, a rise time of the supply voltage may be larger than a time constant of the integrating circuit. In this case, the potential at the node is always equal to the supply voltage. Therefore, the output of the inverter circuit is always at a low level, and so, a reset signal is not outputted at the output terminal.